Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device, which can secure a pattern uniformity.
A dynamic random access memory (DRAM) includes: a plurality of cell arrays each having a plurality of cells arranged therein; and a sub-word line driver (SWD) and a sense amplifier (SA) disposed between the cell arrays. Generally, the cell array is also called a cell matrix.
FIG. 1 is a plan view illustrating a DRAM to describe a basic structure of a cell array.
Referring to FIG. 1, a sub-word line driver (SWD) 103 and a sense amplifier (SA) 104 are disposed between cell arrays 101. For example, a sub-word line driver (SWD) 103 is disposed between cell arrays 101 of a first direction X, and a sense amplifier (SA) 104 is disposed between cell arrays 101 of a second direction Y. A reference numeral 102 denotes a bank. A plurality of cell arrays 101 are disposed in each bank 102.
Each cell array 101 includes a plurality of about 256 K to about 2 M (Mega) cells.
FIG. 2 is a plan view illustrating a detailed structure of the cell array 101 having a plurality of patterns formed therein.
Referring to FIG. 2, a plurality of patterns 105 such as contact holes are formed in the cell array 101.
As the design rule of the DRAM becomes 100 nm or less, it is difficult to form the patterns 105 such as contact holes at an edge 101A of the cell array 101. Accordingly, defects in the edge 101A of the cell array 101 are on the increase.
The conventional method uses one photoresist pattern to form patterns 105 in the cell array 101 including its edge. That is, one mask process and etching process are used to form a plurality of patterns 105. The mask process includes photoresist (PR) coating, exposure and develop processes. Accordingly, there occurs a distortion phenomenon 105A where patterns 105 are not formed at the edge of the cell array 101 or are formed to be smaller at the edge of the cell array 101 than other regions in the cell array 101.
Such distortions in patterning an edge of a cell array in a DRAM fabrication process, that is, in exposing/etching an edge of a cell array, may degrade the output yield of DRAMs according a 30 nm design rule.
A method of forming the pattern at the edge of the cell array to a different size by changing masks several times is mainly used as a method for addressing the distortion phenomenon where the pattern at the edge of the cell array is formed to have a different size from the pattern in the whole cell array.
However, fabricating expensive masks several times may increase the cost of the DRAMs and also reduce the yield of DRAMs because the margin limitation of the current design rule causes a defect in the cells of the cell array edge.